The present invention relates to a write amplifier adapted for dynamic random access memories (DRAMs) and synchronous DRAMs.
Write amplifiers (DQ write amplifiers) and read amplifiers (DQ read amplifiers) are among the most important circuits for implementing high-performance DRAMs. The DQ read/write amplifier is connected to a complementary pair of data lines DQ and /DQ which are large in length and capacitance as compared with bit lines. At data read time, the DQ read amplifier amplifies data which is read from a memory cell, amplified by a sense amplifier, and then outputs it onto the data lines DQ and /DQ. The data amplified by the DQ read amplifier is applied through read/write data buses RWD and /RWD and an input/output buffer to an input/output pad. At data write time, the DQ write amplifier amplifies data supplied through the input/output pad, the input/output buffer, and the read/write data buses RWD and /RWD and outputs it onto the paired data lines DQ and /DQ. The data on the data lines DQ and /DQ is written into a memory cell via a selected sense amplifier. Thus, the DQ read/write amplifier functions as a second sense amplifier.
To perform the above-described operation, the DQ write amplifier requires the following functions:
(1) In the standby state, precharges the data lines DQ and /DQ to a predetermined potential PA1 (2) At write time, drives the data lines DQ and /DQ according to data to be written into PA1 (3) At read time, makes the data lines DQ and /DQ into the floating state.
FIG. 6 shows an example of a conventional DQ write amplifier, which is composed of a precharge circuit and a tri-state write buffer. The precharge circuit, which is constructed from P-channel MOS transistors P3 and P4, precharges the data lines DQ and /DQ to a supply potential Vcc via the transistors P3 and P4 when, in the standby state, a precharge signal /PRCH goes to a low level. At write time, the precharge signal goes to a high level, turning the transistors P3 and P4 off.
The tri-state write buffer is constructed from a P-channel MOS transistor P1 and an N-channel MOS transistor N1 which are connected in series between a power supply terminal 61 supplied with supply voltage Vcc and ground, a P-channel MOS transistor P2 and an N-channel MOS transistor N2 connected in series between a power supply terminal 62 supplied with the supply voltage Vcc and ground, and NAND circuits ND1 and ND2 and inverters I1 and I2 which control those transistors. The data line DQ is connected to the junction of the transistors P1 and N1, and the data line /DQ is connected to the junction of the transistors P2 and N2. The tri-state write buffer is controlled according to a write signal WRITE and data to be written into on write data buses RWD and /RWD. When the write signal WRITE goes high during a write operation, data on the data buses RWD and /RWD are transferred to the data lines DQ and /DQ via the tri-state buffer. To transfer read data from the sense amplifier to a DQ read amplifier during a read operation, the data lines DQ and /DQ are kept floating, the precharge signal /PRCH is set high, and the write signal WRITE is set low. The conventional DQ write amplifier has the following problems.
FIG. 7 shows the operation of the DQ write amplifier of FIG. 6. During a write operation, the precharge signal /PRCH must be set high before the gwrite signal WRITE goes high for cutting DC current. path of the transistors P3 and N1 or the transistors P4 and N2. To realize this, it is required to set a time margin TM between the precharge signal /PRCH and the write signal WRITE. A column select signal CSL goes high almost at the same time the precharge signal /PRCH goes high, connecting the data lines DQ and /DQ to the sense amplifier. For this reason, where the time margin between the precharge signal /PRCH and the write signal WRITE is great, the data lines DQ or /DQ will go low before the write signal WRITE goes high, which delays the write operation and reduces the write speed. Further, since this DQ write amplifier drives the data lines DQ and /DQ of large capacitance, P-channel MOS transistors P1, P2, P3 and P4 of large size are needed. This will lead to an increase in the layout area occupied by this circuit on a chip.